This invention relates to a decoder circuit for use in a semiconductor memory device or the like.
Conventionally, the output of a decoder circuit is controlled by inputting thereto output logic signals of an address buffer circuit. FIG. 1 illustrates one example of a prior art decoder circuit which is constituted by a metal insulator semiconductor field effect transistor (MISFET) Q11 acting as a load and three MISFETs Q12, Q13 and Q14 in parallel connection acting as drivers. The MISFET Q11 is of the depletion type with its drain terminal connected to a power supply Vcc and its gate and source terminals connected in common to a junction N11 leading to an output terminal. The MISFETs Q12, Q13 and Q14 are of the enhancement type. Their drain terminals are connected in common to the junction N11, and source terminals are all connected to ground GND while gate terminals are connected to receive input logic signals A0, A1 and A2, respectively, from an address buffer circuit. For simplicity of description, the decoder shown in FIG. 1 comprises only three MISFETs Q12, Q13 and Q14 acting as drivers, but it should be understood that the number of driver MISFETs may be larger than 3 or equal to two. Furthermore, for the purpose of simplifying the following description, all the MISFETs are of the N-channel type.
The operation of the decoder shown in FIG. 1 will now be described. When at least one of the input logic signals A0 to A2 is at a high level, one of the MISFETs Q12 to Q14 receiving the high level input signal becomes conductive so that the potential at the junction N11 becomes low, whereby the decoder circuit assumes a non-selective state. When all the input signals A0 to A2 are at a low level, all the MISFETs Q12 to Q14 become non-conductive so that the potential at the junction N11 becomes high. Thus, the decoder circuit assumes logic states depending upon the states of the input signals A0 to A2.
In the past, such decoder circuits are connected to respective word lines and selection lines for digit lines of a memory as X-decoders or Y-decoders, respectively, and one of the X-decoders and one of the Y-decoders are energized to select one of the word lines and one of the digit lines, respectively. With such a conventional scheme, however, the field of application of the decoder circuit is inconveniently limited since a plurality of memory cells cannot be selected simultaneously.